1. Technology Field
The present invention generally relates to a flash memory storage system, and more particularly to a data reading method for a flash memory, and a control circuit using the same.
2. Description of Related Art
The growth of digital cameras, camera mobile phones, and MP3 players has been rapid in recent years. Consequently, demands of consumers for storage media of digital contents have increased tremendously. Since a flash memory has a characteristics of non-volatile data, energy saving, compact size, and without mechanical construction, the flash memory is suitable for users to carry on bodies as the storage media for transferring and exchanging the digital contents. Solid State Drive (SSD) is an example of utilizing the flash memory as the storage media, and has been widely applied in the computer host as a main hard disk.
A flash memory may be classified into a NOR flash memory or a NAND flash memory. Additionally, a NAND flash memory may be classified into a Single Level Cell (SLC) NAND flash memory or a Multi Level Cell (MLC) NAND flash memory according to the number of bits which each memory cell thereof is capable of storing. Each memory cell can store one bit of data in a SLC NAND flash memory, and each memory cell can store at least two bits of data in a MLC NAND flash memory. For example, taking a 4 level cell NAND flash memory as an example, each memory cell may store 2 bits of data (i.e., “11”, “10”, “00” or “01”).
In a flash memory, memory cells are linked through bit lines and word lines to form a memory cell array. When a control circuit for controlling these bit and word lines reads/writes data from/to an assigned memory cell, float voltages of other memory cells may be disturbed, and thus error bits may occur (i.e., data (also referred to as “read data”) read from a memory cell by the control circuit is different from data (also referred to as “write data”) originally written into the memory cell). Or, when the flash memory is worn due to some factors (such as, unused for long-teen, leakage of electricity or frequently erased), float voltages of memory cells may change and thus error bits may occur.
In general, an error checking and correcting circuit is configured in a flash memory apparatus for generating an error checking and correcting (ECC) code for data to be written and performing an ECC procedure for data to be read, thereby correcting error bits. Because of manufacturing processes of flash memory or a hardware framework of flash memory, each memory cell can store more and more bits of data and thus the number of error bits occurred in a MLC NAND flash memory may be more than that in a SLC NAND flash memory. Therefore, an error correcting technique capable of correcting more error bits is needed for the MLC NAND flash memory, such as the Low Density Parity Check (LDPC) technique, the Turbo Code technique, and so on. For example, when the LDPC technique or the Turbo Code technique is applied, a memory storage apparatus may obtain soft information from memory cells to try correct more error bits by the LDPC technique or the Turbo Code technique. However, reading soft information will increase greatly the time for executing a read command. For example, according to the disclosure in U.S. patent application NO. 2008/0123408, taking a 4 level cell flash memory as an example, reading data from a upper page and a lower page needs 3 steps, and reading data and soft information from a upper page and a lower page needs 15 steps. Therefore, how to increase the efficiency of reading soft information from memory cells is one of the major subjects in the industry.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.